Project: Ultra High Resolution PLL Synthesizer



Design Services Performed:


This DDS driven PLL synthesizer was designed to allow any input reference to be locked to a 20 MHz master crystal oscillator. This design substitutes two DDS synthesizers for the N and R counters of a standard PLL circuit giving nearly infinite resolution. Spurious performance is the main concern here as the master reference oscillator cannot have any 'extra' spurs on it after locking to the external source. Phase noise of the master reference oscillator was also a major concern in the design as this oscillator is multiplied up many times for the end use microwave instrument. Hence extra effort was put into the design of the DDS dividers and PLL loop shaping to eliminate any spurious signals. Test code was written to allow the synthesizer to be turned on and programmed, thus eliminating extra firmware support from the client.

  • 3 wire serial interface.
  • Reference spur suppression > 90 dBc.
  • Any input of 1 MHz to 20 MHz may be used and locked to a master 20 MHz oscillator.
  • Master oscillator phase noise of 140 dBc / Hz at 10 kHz offset.
  • Self contained low noise, low drift, crystal reference oscillator.
  • RF and PSpice simulations used to verify and optimize the VTXO. and PLL loop filter designs.

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