Description:
In many test systems a
master 10 MHz reference is 'piped' around to all the
measuring instruments and sources. Many instruments do not
use an internal 10 MHz clock, instead some convenient
frequency specific to the particular instrument is used.
Even if the instrument uses 10 MHz internally the external
input is commonly 'cleaned up' with the use of a narrow band
PLL, this helps to eliminate any spurs on the external
reference input. This test circuit was built to prove the
performance of a 10 to 20 MHz clean up oscillator. The
design consists of a low noise, narrow band PLL driving a
precision, voltage tunable 20 MHz crystal oscillator. The
crystal oscillator can thus be locked to the 10 MHz input
while cleaning up any undesirable spurs that may be present
on the input. Test code was written to allow the synthesizer
to be turned on and programmed, thus eliminating extra
firmware support from the client.
- 3 wire PLL
interface.
- Single supply
operation.
- Reference spur
suppression > 90 dBc.
- Phase noise of 140 dBc /
Hz at 10 kHz offset.
- Self contained low
noise, low drift, 20 MHz crystal reference
oscillator.
- PSpice simulations used
to verify and optimize the VTXO design.
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